RT9719 1 ds9719-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wdfn-8l 2x2 sot-23-6 charging system safety device general description the RT9719 is an integrated circuit (ic) designed to replace passive device in charging system with extra protection function. it is optimized to protect low voltage system from up to 28v high voltage input. the ic monitors the input voltage to make sure all parameters are operating in normal range. it also monitors its own temperature and turn off the mosfet when the chip temperature exceeds 140 c. when the input voltage exceeds the threshold, the ic turns off the power mosfet within 1us to remove the power before any damage occurs. user can monitor the adapter input voltage from chrin pin which has 50ma current capability. the gate of the p-mosfet will be controlled by the external charging controller from gatedrv pin if all parameters are operating in normal range. the RT9719 is available in sot-23-6 and wdfn-8l 2x2 tiny packages to achieve best solution for pcb space and total bom cost saving considerations. acin acin isense isense chrin acin gnd 7 6 5 1 2 3 4 8 gnd 9 gatedrv nc gnd acin gatedrv chrin isense 4 23 5 6 marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. features z z z z z no external blocking diode requiring z z z z z overvoltage turn off time of less than 1 s z z z z z high accuracy protection thresholds z z z z z over temperature protection z z z z z high immunity of false triggering under transients z z z z z thermal enhanced sot-23-6 and 8-lead wdfn packages z z z z z rohs compliant and halogen free application z cellular phones z digital cameras z pdas and smart phones z portable instruments RT9719 package type e : sot-23-6 qw : wdfn-8l 2x2 (w-type) lead plating system g : green (halogen free and pb free) ovp default : 6.25v a : 7.20v
RT9719 2 ds9719-01 april 2011 www.richtek.com function block diagram typical application circuit RT9719 acin gnd chrin isense gatedrv v acin c in c out 1f 1f 0.2 soc chrin gatedrv isense vbat 1f battery functional pin description pin no. sot-23-6 wdfn-8l 2x2 pin name pin function 1 -- nc no internal connection. 2 4 gnd analog ground. 3 1, 2, 3 acin the input power source. the vin can withstand up to 30v input. 4 7, 8 isense connect to isense resistor and isense pin of charging controller. 5 6 chrin voltage is equal to vin as vin in power good range and providing ~25ma for system at most. 6 5 gatedrv external control pin for controlling the p-mosfet by charging controller. -- 9 (exposed pad) gnd ground pin. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. control logic mux sw sw inovp uvlo otp acin isense chrin gnd gatedrv
RT9719 3 ds9719-01 april 2011 www.richtek.com electrical characteristics to be continued recommended operating conditions (note 4) z junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v in ------------------------------------------------------------------------------------------------- ? 0.3v to 30v z output (as v in > v out , normal mode) ---------------------------------------------------------------------------------- ? 0.3v to 7v z output (as slee p mode) --------------------------------------------------------------------------------------------------- ? 0.3v to 4.5v z other pins -------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c sot-23-6 --------------------------------------------------------------------------------------------------------------------- 0.556w wdfn-8l 2x2 --------------------------------------------------------------------------------------------------------------- 0.8w z package thermal resistance (note 2) sot-23-6, ja ---------------------------------------------------------------------------------------------------------------- 180 c/w wdfn-8l 2x2, ja ---------------------------------------------------------------------------------------------------------- 125 c/w z junction temperature ------------------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------- 200v (v in = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit power on reset rising vin threshold uvlo 2.5 2.7 2.9 v por hysteresis -- 100 -- mv vin bias current when enable -- 200 600 a reverse leakage i leakage as acin floating -- 5 10 a operation voltage 4.3 -- 6.5 v operation current -- -- 1 a protections RT9719 6 6.25 6.5 v input ovp reference voltage inovp RT9719a 7 7.2 7.4 v input ovp h ysteresis -- 60 100 mv input ovp propagation delay -- -- 1 s otp rising thershold -- 140 -- c otp hysteresis -- 20 -- c
RT9719 4 ds9719-01 april 2011 www.richtek.com note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective single layer thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol conditions min typ max unit power mosfet r ds(on) between acin to isense r ds(on)_isense measure @ 500ma. 4.3v < v in < 6v -- -- 500 m r ds(on) between acin to chrin r ds(on)_chrin measure @ 50ma. 4.3v < v in < 6v -- -- 3
RT9719 5 ds9719-01 april 2011 www.richtek.com typical operating characteristics supply current vs. temperature 0 20 40 60 80 100 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) supply current ( a ) acin = 5v, isense = open, chrin = open, gatedrv = 5v r ds(on) vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) r ds(on) ( ) acin = 5v, isense = 500ma, chrin = open, gatedrv = 0v isense r ds(on) vs. input voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.7 3.1 3.5 3.9 4.3 4.7 input voltage (v) r ds(on) ( ) acin = 5v, isense = 500ma, chrin = open, gatedrv = 0v chrin r ds(on) vs. temperature 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) r ds(on) ( ) acin = 5v, isense = open, chrin = 50ma, gatedrv = 5v chrin r ds(on) vs. input voltage 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2.7 3.1 3.5 3.9 4.3 4.7 input voltage (v) r ds(on) ( ) acin = 5v, isense = open, chrin = 50ma, gatedrv = 5v gatedrv voltage vs. isense current 0 50 100 150 200 250 300 350 400 450 500 2.5 2.7 2.9 3.1 3.3 3.5 3.7 gatedrv voltage (v) isense current (ma) acin = 4.5v, r load = 9.1
RT9719 6 ds9719-01 april 2011 www.richtek.com input ovp recovery delay time (1 s/div) (1v/div) chrin = 1k , gatedrv = acin acin chrin input ovp propagation delay time (500ns/div) (1v/div) chrin = 1k , gatedrv = acin acin chrin ovp vs. temperature 5.00 5.25 5.50 5.75 6.00 6.25 6.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) ovp (v) acin = 5v, isense = open, chrin = 1k , gatedrv = 5v
RT9719 7 ds9719-01 april 2011 www.richtek.com application information operation state the operation state can be shown as following figure 1. at power-off state, the RT9719 will check whether v in is > uvlo threshold. if the v in is higher than the uvlo threshold, the RT9719 will check whether the junction temperature is over the otp threshold. if the junction temperature is higher than the otp threshold, the internal p-mosfet will be turned off. if the junction temperature is lower than the otp threshold, the RT9719 will check whether v in is higher than the ovp threshold or not, if the v in is higher than the ovp threshold, the RT9719 will turn off the internal p-mosfet immediately within 1us. and, if all of the checks including v in > uvlo, t j < otp and v in < ovp are ok, the ic will operate normally. start v in > uvlo t j > otp v in > ovp y yy n n n power-off status otp status pfet=off ovp status p-mosfet = off(fast) normal status p-mosfet = on and control by gatedrv figure 1. operation state diagram for ovp function input over voltage protection (ovp) the RT9719 monitors input voltage to prevent the input voltage lead to output system failures. when the input voltage exceeds the threshold, the RT9719 will turn off the power mosfet within 1us to prevent the high input voltage from damaging the electronics in the handheld system. the hysteresis for the input ovp threshold is 100mv. when the input voltage returns to normal operation voltage range, the RT9719 re-enables the mosfet. the RT9719 allows the input voltage to rise up to 30v without damaging the ic. battery voltage monitor the RT9719 monitors the battery voltage by the isense pin. when the battery voltage exceeds the voltage level of (v acin ? 0.2v), the RT9719 will turn off the mosfet and the battery will not be charged. the RT9719 will recharge the battery when the battery voltage is lower than the voltage of (v acin ? 0.2v). internal over temperature protection the RT9719 monitors its own internal temperature to prevent thermal failures. when the internal temperature reaches 140 c with a built-in hysteresis of 20 c, the ic turns off the power mosfet. the ic does not resume operation until the internal temperature drops below 120 c. input under voltage protection (uvlo) the RT9719 monitors input voltage to prevent the input voltage lead to output system failures. the RT9719 input under voltage protection threshold is set to 2.7v. when the input voltage is under the threshold, the RT9719 will turn off the power mosfet within 1us. when the input voltage returns to normal operation voltage range, the RT9719 re-enables the mosfet. RT9719 acin gnd chrin isense gatedrv v acin c in c out 1f 1f 0.2 soc chrin gatedrv isense vbat 1f battery figure 2. application diagram of RT9719 with soc figure 2 shows the connection of RT9719 in a system diagram. the isense pin of the soc will sense the voltage of the 0.2 sense resistor and the voltage of the vbat pin. the gatedrv pin of the soc can control the mosfet of the RT9719 to determine the level of the charge current. the power of the soc is provided by the chrin pin of the RT9719. the RT9719 provides ovp function, once the input voltage at the acin pin is higher than the ovp level, the RT9719 will be shutdown to prevent the soc from damaging. if the voltage of the battery connected to the vbat pin is full, the RT9719 stops charging by turning off the isense pin. input and output capacitors of 1uf are recommended to place as close to ic as possible. thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between
RT9719 8 ds9719-01 april 2011 www.richtek.com figure 3. derating curves for RT9719 packages layout consideration the RT9719 is a protection device. careful pcb layout is necessary. for best performance, place all peripheral components as close to the ic as possible. a short connection is highly recommended. the following guidelines should be strictly followed when designing a pcb layout for the RT9719. ` the exposed pad, gnd must be soldered to a large ground plane for heat sinking and noise prevention. the through-hole vias located at the exposed pad is connected to ground plane of internal layer. ` acin traces should be wide to minimize inductance and handle the high currents. the trace running from input to chip should be placed carefully and shielded strictly. ` the capacitors must be placed close to the part. the connection between pins and capacitor pads should be copper traces without any through-hole via connection. figure 4. pcb layout guide acin acin isense isense chrin acin gnd 7 6 5 1 2 3 4 8 gnd 9 gatedrv to battery to baseband gate controller input capacitor must be placed between gnd and acin to reduce noise. the capacitor must be placed between gnd and acin to reduce noise. the exposed pad, gnd must be soldered to a large ground plane for heat sinking and noise prevention. from adapter to baseband charger controller c in gnd to battery nc gnd acin gatedrv chrin isense 4 2 3 5 6 to baseband gate controller the capacitor must be placed between gnd and acin to reduce noise. to baseband charger controller from adapter input capacitor must be placed between gnd and acin to reduce noise. c in gnd the exposed pad, gnd must be soldered to a large ground plane for heat sinking and noise prevention. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) sot-23-6 wdfn-8l 2x2 four layouts pcb junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT9719, where t j(max) is 125 c and t a is the operated ambient temperature. the junction to ambient thermal resistance ja for wdfn-8l 2x2 package is 165 c/w and sot-23-6 package is 250 c/w on the standard jedec 51-3 single-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (165 c/w) = 0.606 w for wdfn-8l 2x2 packages p d(max) = (125 c ? 25 c) / (250 c/w) = 0.400 w for sot-23-6 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT9719 packages, the figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.
RT9719 9 ds9719-01 april 2011 www.richtek.com outline dimension a a1 e b b d c h l sot-23-6 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.031 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024
RT9719 10 ds9719-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
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